FMC
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1-Channel DAQ Module
FMC170
Sundance Multiprocessor Technology Ltd.
The FMC170 is an analog-to-digital (A/D) and digital-to-analog (D/A) FMC daughter card that provides one 10-bit A/D channel at 5Gsps and one 10-bit D/A channel at 5Gsps. The sample clock can be supplied externally or by an internal clock source (optionally locked to an external reference). The clock tree enables cascading of multiple boards for phase-locked sampling. A trigger input is also available for customized sampling control.
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FMC, XMC & PMC
The FPGA Mezzanine Card is used by Data Patterns to implement signal interface with external world compatible FPGAs mounted on the FMC carrier there are primarily used for high speed analog interface for digitization (ADCs) and waveform generation (DACs). This form factor is also utilized for special I/O Interfaces such as various avionic protocols and buses. FMC I/O signals may be routed via front panel connectors or through Mezzanine connectors that route the signal back to the carrier board for routing through rear I/O of the Chassis. The system interface is designed for routing to FPGAs using a VITA 57 0.05 Pitch Terminal Array Assembly.
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FMC Dual ADC 12-bit 2.6 GSPS, Single DAC 16-bit 12 GSPS
FMC250
The FMC250 is an FPGA Mezzanine Card (FMC+) per VITA 57.4 specification. The board has dual ADC and single DAC. The FMC250 utilizes dual AD9625 ADCs providing 12-bit conversion rates of up to 2.6 GSPS and a single DAC (AD9162 or AD9164) providing 16-bit conversion rates of up to 12 GSPS. The analog input, digital output, clock and trigger interfaces of the FMC250 are routed via SSMC connectors. The internal clock frequency is programmable and the clock is capable of locking to an external reference.
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PC/104 FFT Processor w. Virtex-5 FPGA
SMT105-FMC
Sundance Multiprocessor Technology Ltd.
The SMT105-FMC can be used either as an I/O-Blade for a Single Board Computer with either the OneBank or Three-Bank PCIe/104™ Connector solution or used as a “Head-Less” solution, ie. Remote Host Controlled.
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FPGA Mezzanine Card
FMC120
The FMC120 provides four 16-bit A/D channels up to 1Gsps, four16-bit D/A channels up to 1.25Gsps and up to 2.8Gsps sample rate with interpolation. The devices can function up to 1Gsps during simultaneously D/A and A/D operation as the clock source is shared.
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product
3U OpenVPX FMC Carrier
VF360
Sundance Multiprocessor Technology Ltd.
The VF360 is a 3U OpenVPX module that leverages on Altera Stratix® V FPGA and Texas Instruments KeyStone Multicore DSP technology to provide an ultra-high bandwidth processing platform, ideally suited for computation and bandwidth intensive applications such as Radar, Networking, SIGINT, EW, SDR and Video.
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Radar Front Ends
FMCW
The transmit signal is derived from an external VCO signal, internally multiplied, which also acts as the LO for the receive mixer. The resulting IF is conditioned for gain and filtering as required. The IF also contains an industry leading IF noise figure, especially in the frequency range below 500MHz. Custom designs available, visit our custom design page for more information.
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Quad 250Msps, 16-bit ADC FMC
ADF-Q25
This FPGA Mezzanine Card (FMC) converts four channels of up to 900 MHz analog input bandwidth at 250 Msps and 16-bit resolution. Based on the VITA 57 specification, the ADF-Q25 enables direct coupling of unparalleled analog-digital conversion capability with the VME/VXS/AMC/VPX/PCI-E carrier board of your choice. DEG engineers have designed this product and associated HDL firmware to work with both Altera and AMD FPGAs.
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Flexible Magnetic Coupler
FMC
The FMC (Flexible Magnetic Coupler) is a partial discharge sensor whose working principle is based on a direct magnetic coupling with the cable conductor and shield.It picks up a magnetic signal given by PD activity. His compact and robust design makes the FMC the optimal sensor for direct installation on cables and accessories such as joints and termination.This sensor has a sensitive side which has to face to the object under test, while the other side (shielded) reject the noise from the environment.
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FPGA Mezzanine Card
FMC165
The FMC165 provides two 14-bit analog-to-digital (A/D) channels supporting RF sampling at 2.6 GSPS and one 14-bit digital-to-analog (D/A) channel with sampling rates up to 5.2 GSPS (2.6 GSPS direct RF synthesis). The converters are clocked by either an internal clock source (optionally locked to an external reference) or an externally supplied sample clock. In addition, a trigger input for customized sampling control is available to users.
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Radar Front Ends (FMCW)
FMCW Series
Farran’s 77 GHz FMCW Radar front end is based on a GaAs MMIC chipset offering wide bandwidth in a small outline package.The transmit signal is derived from an external VCO signal, internally multiplied, which also acts as the LO for the receive mixer. The resulting IF is conditioned for gain and filtering as required. The IF also contains an industry leading IF noise figure, especially in the frequency range below 500MHz. Custom designs available, visit our custom design page for more information.
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FMC for High Speed Optical Communication Dual QSFP+ FMC
FMC424
Sundance Multiprocessor Technology Ltd.
The FMC424 is a dual QSFP+ FPGA Mezzanine Card. Electrically compliant with the VITA 57.1 standard the FMC424 is compatible with 4DSP FPGA carrier cards offering High Pin Count connectors. It also allows for the option to stack an additional FMC over it. Any of the 4DSP FMC that use LVDS and single ended signaling only can be mounted over the FMC424, thus offering users with the ability to build a complete high speed data acquisition, waveform generation and optical communication solution while using a single FMC site on an FPGA carrier card.
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2-Channel DAQ Module
FMC110
Sundance Multiprocessor Technology Ltd.
The FMC110 is a dual channel ADC and dual channel DAC FMC. The FMC110 provides two channels of 12-bit A/D @ 1 GSPS and two channels of 16-bit D/A @ 1 GSPS enabling simultaneous sampling at a maximum rate of 1 GSPS. The sample clock can be supplied externally through a coax connection or supplied by an internal clock source (optionally locked to an external reference). Additionally a trigger input for customized sampling control is available.
