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Verification IP
test and verify SoC's protocols and interface buses.
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IP Performance Testing Tools
Ethernet switches, routers and gateways have their distinct purposes and it is important to test their performance well. During R&D and DVT products are usually tested on L2/L7 while in production basic L2/L3 tests are usually sufficient. For those who follow testing methodology RFC 2544 and RFC 2889 are also available.
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ADSL / 2 / 2+ Handheld VoIP Tester
QuickTest 500
*Rapid Testing. The QuickTest 500 ADSL2+ Tester's automatic Service Verification Test Suite starts as soon as you switch on (results are typically obtained in less than 3 minutes)*Simple to use. Virtually no product training required with QuickTest 500 ADSL Tester*Configurable Pass / Fail Indicators on the LCD display and clearly presented in multi-colour LEDs on the front panel*No need to get a laptop out*Save and name up to 16 test results at any one time*Line Voltage LED indicates poor, missing or excessive Line Voltage*ADSL/2/2+ Test LEDs to indicate if ADSL Showtime achieved*In Service LED indicates problems with PPP or IP layer*LEDs to indicate problems with the Trained Line Rate, poor Noise Margin or excessive Line Attenuation
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Analyze RTL
ASICs and FPGA routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
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MIPI Soundwire Total IP Solutions
Soundwire
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
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Emulation Platform
Veloce
The Veloce® Emulation Platform dramatically reduces risk in the verification of today’s complex SoCs and is a core technology in the Mentor Enterprise Verification Platform™ (EVP). Mentor’s software and application solutions and continual enhancements enable a comprehensive verification environment for IP, chip, and system level verification.
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MIPI Total Display IP Solution
DSI
The Arasan MIPI Display Serial Interface (DSI) Controller IP provides both device and host functionality. Additionally, the DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D-PHY analog IP. Arasan’s DSI solutions are MIPI standards-compliant and are designed to accelerate integration, lower risk and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
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Waterproof Test Chamber
JL-XC
JL-XC series waterproof test chamber is mainly used for small electronic and electrical products. Such as lamps, electrical cabinets, electrical components and so one. The products are tested for physical and other related properties under simulated climatic conditions. After the test, it is judged whether the performance of the product meets the requirements by verification, so as to be used in the design, improvement, verification and factory inspection of the product. Comply with IEC60529:2001 《Degrees of protection provided by enclosures (IP Code)》, GB4208-2008 《Shell Protection Grade (IP Code)》 14.2.8 Terms and GB7000.1 《Lamps Part 1: General Requirements and Tests》 9.2.9 Terms.
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EMBEDDED MMC (EMMC)
SD 3.0 / eMMC 4.51 IP Family
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
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IP Reuse
IC Manage Global Design Platform (GDP & GDP-XL) includes an open platform for maximizing IP reuse. Design and verification teams can use the system to rapidly publish and integrate IP into existing flows, and to trace bug dependencies. Internal and third party IP can be imported or linked with IP Central from multiple commercial and open source design management systems, as well as internal revision control systems. ”
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Ethernet Testing Network Performance
Networked Communication Solutions, LLC
Xena Networks and Veryx Technologies have created an innovative Ethernet test platform that combines Xena’s high performance, wire-speed Ethernet test hardware with Veryx’s broad portfolio of IP & Ethernet functional and conformance test suites. The result: an affordable, high-performance platform for IP & Ethernet load stress, protocol conformance & functional verification testing.
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Field Ttesters
Our product range comprises from small handheld, battery fed testers to full featured service performance assurance tools and distributed monitoring systems. We have several product lines including:QoS / SLA verification system Ethernet, IP, Critical Data, VoIP, IPTV .Hand-held testers: Gigabit Ethernet, Synchronous Ethernet, E1, PDH, SDH, Ethernet, IP, Jitter, Wander, Datacom, Frame Relay, etc.
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IP Networking
We are the industry leader in IP Networking testing. We have a strong and wide-reaching industry reputation and participates in many industry organizations including the IETF, the IPv6 Forum, Open Networking Foundation and NetSecOPEN.
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Verification IP's
SmartDV Technologies India Private Limited
We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP''s are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
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IP QAM
SFT-IPSR3
Hangzhou Softel Optic Co., Ltd.
SFT-IPSR33 is a 2RU rack-mount IPTV streamer server. It is optimal for small and medium internet service providers to initial setup in large network.
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X-Design and Verification System
Ascent XV
The Ascent X-design and verification system (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs from slipping through to silicon.
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PCI Express IP
Rambus silicon-proven, high-performance PCI Express® (PCIe®) 6.0, 5.0, 4.0 and earlier generation digital controllers are optimized for use in SoCs, ASICs and FPGAs. These market-leading solutions for high-performance interfaces address AI/ML, data center and edge applications.
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Functional Verification Platform
Riviera-PRO
Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
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IP / Ethernet Testers
Anritsu's powerful Ethernet/IP network data analyzers incorporate the dual functionality of wire speed performance analysis and network monitoring in the same instrument. Multiple protocols can be decoded and displayed for captured Ethernet, SONET, or SDH frames at full wire speed up to 100 Gbps, augmented by an optional Decode Module and Expert Analysis Module.
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Content Verification System
Pulsar
Pulsar is an automated content verification system for stored media files. It is designed for use by Broadcasters, Service Providers, Content Creators and Optical Media replicators allowing them to analyze the content before it is put live or stamped on the optical media. The software performs conformance and quality analysis on the streams provided. It allows definition of a range of user-defined checks to be performed as part of the Analysis.
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IC Design & Verification
Mentor Graphics provides best-in-class products for IC design. Calibre for physical verification, extraction, resolution enhancement and mask data preparation, ADVance MS for analog/mixed-signal simulation and an integrated tool flow for custom IC design
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Verification And Validation Services
Verification and validation services using innovative verification and validation techniques throughout the entire quality process for independent evaluation of performance and quality of product designed.
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IP to Dual RS-232 Controller
VSA-31-IP
The VSA-31-IP is an add-on module for the Switch-Cat A/V Systems. The new IP module allows monitoring and control of one to multiple Switch-Cat installations via IP across the customers internal network.
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IP code Testing
Educated Design & Development, Inc.
Complies with various IEC, EN, CE, VDE, UL & CSA requirementsUnit comes with NIST traceable / ISO 17025 accredited certificate of calibration.ED&D is ISO 17025 accredited by ACLASS, an ILAC Member. Measurement data and uncertainty data is available.Uses RTS-01 Rain Spray Head
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Barcode Verification Systems
REA ScanCheck 3
The REA ScanCheck 3 is an universal, battery-operated, high-performance barcode verification device which operates in accordance with current standards. The verifications document compliance with quality goals in production and monitoring of barcodes on data storage devices and products of all kinds. The measurement principle is based on a laser scanner optimized for verifications. This makes contact-free measurement, largely independent of handling influences, possible. For mobile use on site, the device operates self-sufficiently, independent of the power network with standard, rechargeable batteries. The operating system and application software support multiple languages.
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Resistivity and IP Imaging System
ARES
ARES represents a well equipped resistivity and IP imaging system. Groundwater explorations, geotechnical investigations, monitoring of dams and dikes, environmental studies, pollution plumes mapping, geological surveys, mineral prospecting, archaeology, detecting of cavities, underwater, marine, borehole and cross-hole measurements.
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Test Program Quality Verification
CodeReport
CodeReport is an easy-to-use application for verifying test program quality. CodeReport comes with many different, known quality screening rules that can be used to verify your test program is complete and ready for production. CodeReport also provides a graphical Rule Editor that allows you to create your own, custom rules. Ensure your coding standards and quality specifications are correct by generating your set of rules, checks, and screenings. Easily generate a detailed report for locating, correcting, and documenting the state of your test program. Quickly identify the tester hardware and instrumentation needed to run your program with the Tester Resource report. Save a session file to quickly return to your project after edits have been made or use the Session on other similar projects to transfer your configuration and custom rules.
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IP Fax/ Modem Testing
To successfully deploy fax services requires extensive network design, test and traffic engineering. Test equipment can prove valuable in this process, if it can: Generate and receive fax signals in bulk over wired and wireless networks, monitor and distinguish fax signals in real time for traffic engineering and network design purposes, and analyze fax signals after capture for troubleshooting failed or poorly handled calls.
