Memory Test System
T5230 - Advantest Corp.
T5230 memory test system for NAND/NVM devices adopts a combined array architecture to achieve best-in-class cost-of-test performance for wafer test, including wafer-level burn-in (WLBI) and built-in self-test (BIST). The system can perform on-wafer test of 1,024 memory devices per test head in parallel, delivering high productivity and enabling floor space savings of up to 86%. Multiple test cells are connected per system controller in the T5230, allowing independent wafer test of each test cell. The test cells can be stored in a general multi-wafer prober while minimizing the test cell floor space, and the tester can be docked with probers in both linear and multi-stack configurations. For functional tests at a maximum test rate of 125MHz/250Mbps, the T5230 assures high timing accuracy, repeatability, and failure detection capability.
Topics
- Test Systems
- Memory Test Systems
- Test
- Testing
- Systems
- Memory
- Performance Testing
- Functional Test
- Memory Device
- Test Heads
- Polarization Extinction Ratio
- Probers
- Space
- Wafer
- Arrays
- BIST
- Burn-In
- Combiners
- Control
- Controllers
- Detection
- Failure
- Generators
- Heads
- Linearizer
- Parallel
- Repeaters
- Testers
- Time
- Timing
- Control Systems
- System Test
